`timescale 1ns / 1ps

module change_value(
    input   wire             sys_clk   ,
    input   wire             reset_n   ,
    input   wire             begin_flag,

    input   wire     [2:0 ]  grade      ,
    input   wire     [23:0]  seta_1_in  ,
    input   wire     [23:0]  seta_2_in  ,
    input   wire     [23:0]  seta_3_in  ,
    input                    dir        , // 
    input                    tan_sign   , // 抓取目标的方位 1:目的地 0:仓库

    output  reg      [11:0]  angle_1    ,
    output  reg      [11:0]  angle_2    ,
    output  reg      [11:0]  angle_3    ,
    output  reg      [11:0]  angle_4    ,

    output  reg              finish_flag
);

parameter   one_th_five_han   = 12'd1500;
// 误差值
// parameter   S1_pi             = 24'd677205; // 10.333
// S0
parameter   S1                = 4'b0001;
parameter   S2                = 4'b0010;
parameter   S3                = 4'b0100;
parameter   S4                = 4'b1000;

/* 乘法模块 */
reg  [23:0]	    mux_a_in;
wire [15:0]	    mux_y_out;

reg  [3:0]      cnt;
reg             angle_sign;
wire [11:0]     angle_zheng;

assign angle_zheng = angle_sign ? (one_th_five_han - mux_y_out[11:0]) : (one_th_five_han + mux_y_out[11:0]);

always@(posedge sys_clk or negedge reset_n) begin
    if(!reset_n) begin
        angle_4 <= 1'b0;
    end else begin
        casex(grade)
        3'd0:begin
            angle_4 <= angle_1;
        end
        3'd1:begin // 逆时针旋转小角度
            angle_4 <= angle_1 - 12'd333;
        end
        3'd2:begin // 逆时针旋转大角度
            angle_4 <= angle_1 - 12'd500;
        end
        3'd3:begin // 顺时针旋转大角度
            angle_4 <= angle_1 + 12'd400;
        end
        3'd4:begin // 顺时针旋转小角度
            angle_4 <= angle_1 + 12'd200;
        end
        endcase
    end
end

always@(posedge sys_clk or negedge reset_n) begin
    if(!reset_n) begin
        cnt <= S1;
        finish_flag <= 1'b0;
        mux_a_in    <= 1'b0;
        angle_sign  <= 1'b0;
        angle_1     <= 1'b0;
        angle_2     <= 1'b0;
        angle_3     <= 1'b0;
    end else begin
        casex (cnt)
        S1:begin
            mux_a_in   <= seta_1_in;
            angle_sign <= tan_sign ? !dir : dir; // 目的地与仓库 tan_sign = 1（目的地） : 1(负区域) :0

            finish_flag <= 1'b0;
            if(begin_flag) cnt <= S2;
            else cnt <= S1;
        end
        S2:begin
            angle_1 <= angle_zheng;

            mux_a_in <= seta_2_in; 
            angle_sign <= tan_sign; // 1:目的地 0:仓库 
            cnt <= S3;
        end
        S3:begin
            angle_2 <= angle_zheng;

            mux_a_in <= seta_3_in;
            angle_sign <= !tan_sign; // 0:目的地 1:仓库
            cnt <= S4;
        end
        S4:begin
            angle_3 <= angle_zheng;

            finish_flag <= 1'b1;
            cnt         <= S1  ;
        end
        default: cnt <= S1;
        endcase
    end
end

mult2	mult2_my_inst (
	.dataa ( mux_a_in ),
	.result ( mux_y_out )
);

endmodule
